1. Industrial Field of the Invention
The present invention relates to a multilayered interconnection substrate and to a process for fabricating the same. More specifically, the present invention relates to fine contact structures of multilayered interconnection substrate represented by thin film transistor substrates and the like.
2. Prior Art
Referring to FIG. 6, a contact structure of a prior art multilayered interconnection substrate is explained briefly below. A lower interconnection 102 is patterned into a predetermined shape and provided on the surface of an insulation substrate 101. The surface of the lower interconnection is entirely covered by at least two layers of insulation films 103 and 104 differing from each other in composition. An upper interconnection 105 patterned into a predetermined shape is provided further thereon. An intermediate interconnection (not shown in the figure) is formed between the two layers of the insulation films 103 and 104. A contact hole 106 is formed through the two layers of the insulation films 103 and 104 to partially expose the lower interconnection 102 at the bottom of the contact hole 106. The upper interconnection 105 is electrically connected to the lower interconnection 102 via the contact hole 106 to establish the electrical connection between the interconnections.
The problems to be solved by the present invention is described briefly below. From the viewpoint of process design, the insulation film 103 is sometimes made of a material differing from that used in the insulation film 104. The two layers of insulation films 103 and 104 are locally perforated by means of, for example, wet etching, to establish the contact hole 106. To make the process simple, the two layers of insulation films 103 and 104 are continuously subjected to wet etching using a common processing solution. In the process, the etching rate for the two insulation films 103 and 104 differs according to the difference in their composition. As is shown in the figure, side etching proceeds in case the etching rate for the lower insulation film 103 is set higher than that for the upper insulation film 104. Thus, in such a case, the contact hole 106 forms in a reverse tapered shape. That is, a void 108 is produced just under the overhanging portion 107 of the upper insulation film 104. The upper interconnection 105 in a contact structure of this reverse tapered shape is apt to cause breakage at steps and the like along the void 108. This leads to the problematic generation of contact failure. The two insulation films can be prevented from being etched in a reverse tapered shape by selecting such a material having an etching rate higher than that of the lower insulation film 103 for the upper insulation film 104. However, the use of selected materials restricts the freedom in material design, and, from the viewpoint of process design, it also disadvantageously limits the selection of etching solutions. Moreover, it is practically impossible to completely prevent side-etching from occurring because the etching rate differs from time to time due to the local fluctuation in composition of the insulation films 103 and 104.